1. Field of the Invention
The present invention relates to on-chip fault diagnosis of semiconductor memory devices, such as built-in self test (BIST) techniques.
2. Description of the Related Art
The BIST architecture, in which a memory device is designed to test itself, is well-known in the art. As disclosed in Japanese Laid Open Patent Application JP-A 2000-276898, one requirement on the BIST architecture is to identify error addresses and to identify data read from the error addresses. Information on the error addresses and the data read from the error addresses provides an important basis for analyzing the cause of fault of the memory device.
One issue of the BIST architecture is that storing all the error addresses within the memory device to be tested requires an increased circuitry overhead. As disclosed in Japanese Laid Open Patent Application No. JP-A-Heisei 11-16392, an approach for reducing the circuitry overhead is to externally output the error address each time an error is found.
FIG. 1 is a structure of a memory device adopting such BIST architecture. A memory device is composed of a fault diagnosis circuit 100 and an RAM 102, which are monolithically integrated within a single semiconductor chip. The fault diagnosis circuit 100 is designed to perform on-chip test of the RAM 102. The RAM 102 is composed of a plurality of addressable memory cells. When a write request is issued, the RAM 102 receives and stores externally-inputted data onto a memory cell associated with the write address. When a read request is issued, the RAM 102 outputs data stored in a memory cell selected by the read address.
The fault diagnosis circuit 100 includes an address generator 103, an expected data generator 104, a comparator 105, and a test result register 106.
The address generator 103 generates and updates the test address of the RAM 102. The update of the address is synchronous with a clock; the address generator 103 increases the test address for each clock cycle. The address generator 103 is designed to stop updating the test address when being instructed by a control signal 107 received from the comparator 105. The address generator 103 is typically composed of a counter.
The expected data generator 104 develops expected data for each address to be tested.
The comparator 105 compares data received from the RAM 102 with the expected data received from the expected data generator 104. When the data received from the RAM 102 matches the expected data, the comparator 105 activates the control signal 107 to indicate the address generator 103 to stop generating the address.
The test result register 106 is designed to store the comparison result between the data received from the RAM 102 and the expected data. The test result register 106 is designed to be externally accessible through a signal line 108. The test result register 106 externally outputs the comparison result through the signal line 108.
The fault diagnosis circuit 100 is designed perform test on each address of the RAM 102. When no error is found on a specific test address, the fault diagnosis circuit 100 updates the test address to the next address. When an error is found, the fault diagnosis circuit 100 stops updating the test address.
One drawback of this test procedure is that a speed dependent error may be overlooked. The aforementioned test procedure interrupts the test at a certain address when an error is found, and the subsequent test is resumed from the address at which the test is interrupted. This results in that the test address is not updated at constant time intervals, and the RAM 102 is partially tested at a reduced frequency. Testing the RAM 102 at a reduced frequency may undesirably lead to an overlook of a speed dependent error.
Another drawback of the above-described test procedure is that a considerably long duration is necessary for transferring the test result from the memory device to an external tester. When the tested RAM 102 is a DRAM, the duration required to extract the test result may exceed the refresh cycle. This undesirably results in that a normal address may be incorrectly detected as an error address.
Therefore, there is a need for providing on-chip fault diagnosis architecture which allows detection of speed dependent error within memory devices with a small circuitry overhead.
Japanese Laid Open Patent Application JP-A-Heisei 11-16393 discloses a self test circuit designed to output fail bit map information within a reduced time duration. The self test circuit is composed of an error address detector for detecting an error address, and a data compression device for compressing error address information. The compressed error is externally outputted to an external tester.